#12: Shift Registers
- Read Chapter 13 of William Kleitz's Digital
Electronics: A Practical Approach with VHDL (9th edition).
- Turn in solutions to Problems 13–1, 13–2*,
13–3*, 13–6, 13–7, 13–8, 13–9, 13–10**,
13–18***, 13–19***, 13–20***, 13–21***, 13–31,
and 13–33 on pages 668 to 678.
- *Hint for Problems 13–2 and 13–3: Remember that the
SD inputs are active-LOW.
- **The figure for Problem P13–10 contains a typo:
The last pulse on Q0 should
rise on the falling edge of clock pulse 9, not on the rising edge
of clock pulse 10.
a straight-edge for these timing-diagram problems. If you don't want to
redraw all of the input waveforms by hand, print
these pages and draw the output waveforms only.