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Errata: Suspected Typos in Stephen Brown & Zvonko Vranesic's Fundamentals of Digital Logic with VHDL Design (3rd edition, 7th printing)


p. 67, sixth line: "use M11 again" should be "use M9 again," and on the next line, "to derive M11" should be "to derive M9."

p. 200, seventh line of Example 4.9: "still four inversions" should be "still five inversions."

p. 278, first line of first full paragraph: "section 5.3.5" should be "section 5.3.6."

p. 297, second line of last paragraph: "and Electronic" should be "and Electronics." The same change should be made in Reference 3 on p. 316.

p. 337, second line: "problem 6.32" should be "problem 6.36."

p. 344, first line of first full paragraph: "m0, . . . , m3" should be "m(0), . . . , m(3)."

p. 347, sixth line of Example 6.15: "the value of f " should be "the value of y."

p. 360, fifth-to-last line of code in Figure 6.47: to match Figure 6.25, "1110011" should be "1111011." (Either value will display a 9, but one with a tail and one without a tail.)

p. 366, second line of Example 6.27: "f(w1, w2, w3, w4)" should be "f(w1, w2, w3, w4, w5)." Similarly, on the second line of the next page, "w3, and w4" should be "w3, w4, and w5."

p. 367, fifth line of the Solution to Example 6.27: the last term of the expression for f should be "w1w4(1)" instead of "w1w2(1)."

p. 369, last line of the Solution to Example 6.30: the second term of the expression for f should be "s1kw2" instead of "s1kw3" and the third term should be "s1kw3" instead of "s1kw4."

p. 372, fourteenth line of code in Figure 6.57: This line of code ("SIGNAL High : STD_LOGIC;") can be deleted since the signal it declares (High) is not used anywhere. (Presumably this signal was originally used in the PORT MAP three lines later, since VHDL 1987 did not allow the use of the literal value '1' in a port map. But VHDL 1993 does allow such use of literals, rendering the signal High unnecessary.)

p. 372, fifteenth line of code in Figure 6.57: "SIGNAL y : STD_LOGIC_VECTOR(3 DOWNTO 0)" should be "SIGNAL y : STD_LOGIC_VECTOR(0 TO 3)." The original code will compile but will produce incorrect results since the range of the signal y does not match the range of y in the PORT MAP three lines earlier. For example, the original code will assign w(2) to f when s=1 and will assign w(1) to f when s=2. Changing the range of y as noted above will fix this, assigning w(1) to f when s=1 and assigning w(2) to f when s=2.

p. 374, ninth-to-last line of code in Figure 6.59: "IF shift = "1" " should be "IF shift = '1' " (i.e., replace the double quotation marks with single quotation marks). Also make a similar change in the fourth-to-last line of this code: "k <= "0" " should be "k <= '0' ".

p. 487, second line after numbered list: "on its input(s)" should be "on their input(s)."

p. 788, second-to-last line of Figure A.2: "SIGNAL]" should be "[SIGNAL]." The same change should be made to the second-to-last line of Figure A.6 on page 792.

p. 827, third-to-last line: "and generate statements" should be "conditional signal assingments, and generate statements."

p. 829, second line after first code example: "Also, it is illegal" should be "Also, in VHDL 1987 (but not in later versions), it is illegal."