- Read Sections 6.1 and 6.2 of Brown & Vranesic's Fundamentals of Digital
Logic with VHDL Design (3rd edition). Also refer to Section 6.8 for examples of solved problems, some of which are similar to problems assigned below.
- Print and turn in these timing
diagrams. Also turn in solutions to the following Problems at the end of Chapter 6:
- Problems 6.1 and 6.2
- Problems 6.3 and 6.4, but change the wording of these problems to say "4-to-1 multiplexer" instead of "2-to-1 multiplexer." And since I'm changing the wording of these problems, the book's answer to Problem 6.3 is no longer appropriate. Rather, see below for a correct answer to Problem 6.3.
- Don't forget to complete the timing
diagram sheet mentioned above, which has additional problems that are not from the textbook.
- For the starred problems, check yourself against
the answers given at the back of the book (starting on page 919), except since I changed the wording of Problem 6.3, a correct answer is: