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Errata: Suspected Typos in M. Morris Mano & Michael D. Ciletti's Digital Design: with an Introduction to the Verilog HDL (5th edition, 1st printing)


Most of the typos listed here have been fixed in the 6th edition. Click here for a list of suspected typos in the 6th edition.

p. xiii, first bulleted item: "in the test" should be "in the text."

p. 2, last line of first full paragraph: "of a analog" should be "of an analog."

p. 5, sixth line: "0000" should be "1111."

p. 8, eighth line of Example 1.4: "to seven significant" should be "to six significant."

p. 23, ninth line: "The 9's complement of 604 is" should be "Its 9's complement, 604, is."

p. 36, Problems 1.35 and 1.36: Since these problems deal with gates that are not introduced until Chapter 2, they should be moved to the end of that chapter.

p. 42, last line of item number 5: "postulate 1 is verified" should be "postulate 5 is verified."

p. 45, second-to-last line of Theorem 6(a): "2(a)" should be "theorem 2(a)", so that the reader will not assume it to mean postulate 2(a).

p. 52, tenth line: the expression for f1 should contain another maxterm, namely (x+y'+z').

p. 53, second-to-last line of Example 2.4: In the expression for F, there should be a prime on C in the second minterm: i.e., " AB'C " should be " AB'C' " .

p. 54, first line: "A = 1 and BC = 01" should be "A = 1 or BC = 01."

p. 57, Figure 2.3(b): the third input to the 3-input OR gate should be z' instead of z.

p. 62, last line of the last full paragraph: "Section 3.7" should be "Section 3.6."

p. 63, sixth line: "Section 3.9" should be "Section 3.8."

p. 68, fourth-to-last line: "Electronics and Electrical" should be "Electrical and Electronics."

p. 68, third-to-last line: "Section 3.10" should be "Section 3.9."

p. 77, ninth line: in the expression for m4 + m6,  " xz' + (y' + y) " should be " xz' · (y' + y) "; i.e., change the OR to an AND.

p. 87, ninth-to-last line: "Section 2.6" should be "Section 2.7."

p. 91, fourth-to-last line: "OR-invert" should be "invert-OR."

p. 97, second-to-last line: " (AB)' · · · (CD)' " should be " (AB)'(CD)' ", i.e., delete the three dots.

p. 99, fifth line: "Section 3.5" should be "Section 3.6."

p. 115, second line: "Fig. 4.36" should be "Fig. 4.34."

p. 115, last line: "(&), (/), and (~)" should be "(&&), (||), and (!)" .

p. 117, HDL Example 3.5: In the second comment line, "D 5 f(A,B,C) 5 Σ" should be "D = f(A,B,C) = Σ" . Also, in the comment for the second-to-last line, "Option gate" should be "Optional gate."

p. 132, Figure 4.3: in the lower-left map (i.e., the map for x), the cell labeled m6 should be empty instead of containing a 1.

p. 140, second line: in the equation for C3, the last "=" should be a "+" .

p. 141, Figure 4.12: on the top input wire into each of the XOR gates for S3, S2, and S1, delete the dot indicating a wire-junction point; and delete the short horizontal wire segment coming in to the left side of these dots for the S3 and S2 gates. Also, the bottom input wire into the XOR gate for S0 should not be attached to the Carry Lookahead Generator; rather, it should be routed below the Carry Lookahead Generator and should attach to the C0 input wire.

p. 149, seventh-to-last line: in the equation for (A < B), " x3x2A'1B'1 " should be " x3x2A'1B1" (delete the prime on B1); and " x3x2x1A'n0B'0 " should be "x3x2x1A'0B0 " (delete the n and delete the prime on B0).

p. 152, Figure 4.19(b): the entry in the last column of the truth table's last row should be a 0 instead of a 1.

p. 164, first line of Section 4.12: "Section 3.10" should be "Section 3.9." The same change should be made on this page's third-to-last line.

p. 166, fourth-to-last line: "Section 3.10" should be "Section 3.9."

p. 171, fifth line: "Section 8.2" should be "Section 8.3."

p. 172, second line: "input port" should be "input or output port."

p. 172, eleventh line: in the assign statement, "(B && S)" should be "(B && !S)" .

p. 172, HDL Example 4.3: In the equation for D[1], "!(*!A)" should be "!((!A)" . Also, in the equation for D[2], "B" should be "!B", and the line should end with another right parenthesis followed by a comma. Also, the equation for D[3] should end with a semicolon.

p. 174, fourth, fifth, and second-to-last lines: "OUT" should be "m_out."

p. 175, second-to-last line of HDL Example 4.7: "m_out 5 B" should be "m_out = B."

p. 175, second line after HDL Example 4.7: "output y" should be "output m_out."

p. 176, fifth line: " d' o', and h' " should be " 'd, 'o, and 'h " .

p. 179, fourth line: Insert " B = %b " after " A = %b " .

p. 179, last line of HDL Example 4.9 on this page: "t_m_out" should be "t_mux_out."

p. 180, last five lines of HDL Example 4.9: According to these lines, time is the last quantity displayed on each line of the simulation log, but actually time is the first quantity displayed on each line.

p. 180, eighth line after HDL Example 4.9: "Section 3.10" should be "Section 3.9."

p. 180, last two sentences of the first paragraph: These sentences, beginning with "A $monitor system task," refer to the previous HDL Example (4.9) and therefore should be placed at the beginning of this paragraph rather than in their current location, where they seem to refer to HDL Example 4.10.

p. 181, HDL Example 4.10: in the repeat statement, "D 1 1'b1" should be "D + 1'b1" .

p. 183, Problem 4.9: "An ABCD" should be "A BCD" .

p. 204, Figure 5.14: The function table should be labeled as part (c) of this figure rather than part (b). Also, the entries in the first column of the function table's last two rows should be 1 instead of 0.

p. 205, Figure 5.15: Delete the 3-input OR gate, the NOT gate connected to it, and all wires connected to these two gates.

p. 206, fourteenth and fifteenth lines: the — sign in each of these expressions should be an = sign.

p. 208, last line: "Equations — State" should be "Equations → State" .

p. 213, fifth line: "JA and KA" should be "JA and KA" .  And in the next line, "JB and KB" should be "JB and KB" .

p. 220, second-to-last line: "blocking" should be "nonblocking."

p. 223, second line of HDL Example 5.3 on this page: "output reg Q" should be "output Q."

p. 225, continuation of HDL Example 5.5 from previous page: Several of these lines are superfluous but harmless. In particular, the lines "#70 t_x_in=1;" and "#70 t_x_in=0;" cancel each other and therefore have no effect on the simulation. Likewise the line "#90 t_x_in=1;" has no effect, since t_x_in already has a value of 1 at the time in question. Also, the lines "#160 t_x_in=0;" and "#170 t_x_in=1;" have no effect on the output shown in Figure 5.22 (on page 226), since they refer to times that are off the right-hand edge of this figure.

p. 225, first line after HDL Example 5.5: "circuit I HDL" should be "circuit in HDL."

p. 225, third-to-last line: "both to state[1:0]" should be "both state[1:0]."

p. 226, Figure 5.22: From time=0 to time=10, the waveform for t_x_in should be undefined rather than low. Also, in the text at the bottom of the figure, "alid Mealy" should be "Valid Mealy" . Also, the arrow by the words "Mealy glitch" points to the wrong place; it should point to the third pulse in the t_y_out waveform, not the second pulse.

p. 226, second line after Figure 5.22: "from 0 to 1" should be "from S1 to S0."

p. 227, HDL Example 5.6: In the title line for this example, delete the words "Zero Detector."

p. 228, Figure 5.23: Assuming that this figure is generated using the same test bench as the previous Figure, then from time=0 to time=10, the waveform for t_x_in should be undefined rather than low. If t_x_in were truly low during this interval, then state and t_y_out would change from 0 to 1 at the first rising edge of clock.

p. 228, first line of second paragraph: "zero detector" should be "binary counter."

p. 230, fifth and sixth lines: both instances of "Toggle_flip_flop_3" should be "Toggle_flip_flop."

p. 230, twenty-first line: "negedge RST" should be "negedge RST_b."

p. 244, Table 5.14: the entry in the second-to-last column of the second-to-last row should be 0 instead of 1.

p. 261, last line of first full paragraph: "Section 4.4" should be "Section 4.5."

p. 262, first line of first full paragraph: "Section 4.4" should be "Section 4.5."

p. 270, second-to-last line: "set if J = 1" should be "set if J = 1 and K = 0." Also, "cleared if K = 1" should be "cleared if K = 1 and J = 0."

p. 271, last line of first paragraph: "next transition" should be "next 1-to-0 transition."

p. 271, second line of second paragraph in Section 6.4: "Fig. 5.31" should be "Fig. 5.32."

p. 278, fourth line of first full paragraph: "A0" should be "A1"; also, "from 1010 to 1011" should be "from 1001 to 1010."

p. 284, third line: "Table 6.6" should be "Table 6.3."

p. 284, ninth line: "two serial inputs (shift_left, shift_right)" should be "a clock input, and a clear input."

p. 286, fifth line: "assign [1:0]" should be "wire [1:0]" .

p. 287, fourth line of HDL Example 6.2 on this page: "Clr" should be "Clr_b" .

p. 299, third line of third paragraph: "process is referred" should be "process referred."

p. 303, third line after Table 7.1: "the word operation" should be "the read operation."

p. 312, fifth line of Section 7.4: "Section 3.9" should be "Section 3.8."

p. 313, fourth line: "(3, 5, 7, 10, 11)" should be "(3, 6, 7, 10, 11)."

p. 316, ninth line: "Fig. 6.1" should be "Fig. 7.1."

p. 324, third-to-last line: "because F1 is" should be "because F1' is."

p. 334, fifth line of second paragraph: Delete the sentence that says "The other element can get an external input from the H1 input."

p. 335, Figure 7.22: On the lower 4-input multiplexer, the inputs labeled F', G', and H' should be labeled G', H', and F', respectively.

p. 352, tenth-to-last line: "copied to R1" should be "copied to R2."

p. 355, last line: "arithmetic, logic, and shift" should be "arithmetic, bitwise or reduction, and shift."

p. 357, second line of indented section: "(1010) & (1010)" should be "(1010) & (0000)."

p. 367, sixth line after Figure 8.5: "= 0" should be "= 1."

p. 373, Figure 8.9(a): For consistency with the subsequent discussion of this circuit and with HDL Example 8.2, the wire labeled reset_b should be connected only to the Controller box, not also to the Datapath box.

p. 376, fourth-to-last line: "clr_E. Depending" should be "clr_E, depending" (i.e., the period should be a comma). Also, on the next line, "is asserted, set_F" should be "is asserted. set_F" (i.e., the comma should be a period).

p. 378, Figure 8.11(b): Before the last line, insert a line showing that A is to be incremented when the state changes from S1 to S2: "S_1 → S_2incr_A:      ← + 1"

p. 380, Figure 8.12: The lower output on each of the D flip-flops should have a bubble to identify it as a complemented output.

p. 388, third line of first full paragraph: "DG1 and DG0" should be "D_G1 and D_G0." The same change should be made in the fourth-to-last line of this paragraph.

p. 391, first line of the indented section: "multiplican" should be "multiplicand."

p. 394, fourth line: Delete the sentence that says "Initially, the multiplicand is in B and the multiplier in Q" since it's not true that these values are initially in B and Q; rather, as is stated in the first line of the next page, the values are loaded into these registers when the state changes from S_idle to S_add.

p. 397, Figure 8.16(b): Add the following to the Register Operations column of the state transition from S_idle to S_add: B <= Multiplicand, Q <= Multiplier.

p. 399, first line after Table 8.7: "state" should be "state or the outputs."

p. 401, third-to-last line: "three flip-flops" should be "two flip-flops."

p. 403, footnote: "dp-width" should be "dp_width" (underscore instead of hyphen).

p. 404, first case of the case statement about halfway down the page: "begin if (Start) next_state" should be "if (Start) begin next_state." Here's why: the code as given in the text asserts Load_regs unconditionally whenever we're in state S_idle. While this will produce correct multiplication results, it's inconsistent with the ASMD chart in Figure 8.15(b), according to which Load_regs is asserted only if we're in state S_idle and Start = 1. The code as given in the book also has the undesirable effect of loading a new multiplier into Q as soon as we re-enter S_idle, rather than leaving the previous result in Q until we're ready to start a new multiplication.

p. 407, Figure 8.19: In the first of the two waveforms labeled Product[9:0], "2j3" should be "2f3"; also, "11b" should be "116" .

p. 409, sixth line of HDL Example 8.6 (continued from previous page): "5 Multiplicand" should be "#5 Multiplicand."

p. 421, second line of HDL Example 8.8 (continued from previous page): This declaration of R2 as a wire is harmless but serves no purpose unless R2 is assigned a value elsewhere, which it is not. The simulation result in Figure 8.24 shows R2 being equal at all times to count, but with the given code, R2 will actually be undefined at all times.

p. 423, sixth line after Figure 8.24: "blocked" should be "blocking." The same change should be made on the tenth line of this page, and on the following lines of page 424: second line, second line of second paragraph, tenth line of second paragraph, and eleventh line of second paragraph.

p. 446, last line before Truth Tables subsection: "Section 3.7" should be "Section 3.6."

p. 447, bullet item (e): "Fig. 3.32" should be "Fig. 3.30."

p. 448, fourth line of Section 9.4: "Section 3.7" should be "Section 3.6."

p. 450, fourth line: "Section 3.9" should be "Section 3.8."

p. 454, Figure 9.9 caption: "38 × 1" should be "8 × 1."

p. 467, fourth-to-last line: "is A and" should be "is A0 and."

p. 473, tenth line of IC Timer subsection: Delete "(See Section 10.3)."

p. 475, Figure 9.22: both instances of "µS" should be "µs" (lower-case s).

p. 481, Figure 9.24(d): Add the following to the Register Operations column of the state transition from S_idle to S_add: B <= Multiplicand, Q <= Multiplier.

p. 483, second line of Supplement to Experiment 2 subsection: "Section 3.10" should be "Section 3.9." Also, in the last line of this paragraph, "Fig. 3.38" should be "Fig. 3.36," and on the line after that, "Fig. 3.32(a)" should be "Fig. 3.30(a)."

p. 486, last line: "part (b)" should be "part (d)"; also, "part (a)" should be "part (b)."

p. 487, second line: "Section 8.7" should be "Section 8.9"; also, four lines after that, "Section 8.5" should be "Section 8.6."

p. 495, seventh line: "EN is active" should be "EN is inactive."

p. 496, fourth line of second paragraph: "741551 IC" should be "74151 IC."

p. 498, third line after Figure 10.8: "Fig. 6.5" should be "Fig. 5.6"; also, on the next line, "Fig. 6.9" should be "Fig. 5.9," and "Fig. 6.12" should be "Fig. 5.10."

p. 501, seventh line: "M1" should be "M2."

p. 501, last line: "= 10" should be "= 01."

p. 505, Figure 10.15: Inside the RAM block where input line A3 attaches, "2" should be "3."

p. 515, Figure A.8: in the second column of the truth table, the entries in the last two rows should be 0 and 1, respectively, instead of 1 and 0.