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Errata: Suspected Typos in M. Morris Mano & Michael D. Ciletti's Digital Design: with an Introduction to the Verilog HDL, VHDL, and SystemVerilog (6th edition, 1st printing)


Click here for a list of suspected typos in the 5th edition, most of which have been fixed in the 6th edition.

p. 11, Answer to Practice Exercise 1.3: "1110 00012" should be "1000 01112."

p. 11, Answer to Practice Exercise 1.4: "7028" should be "2078."

p. 16, second line of Answer to Practice Exercise 1.6: "43106310" should be "4310= 6310."

p. 16, first line of Practice Exercise 1.7: "Repeat Practice Exercise 1.6" should be "Repeat Practice Exercise 1.5."

p. 26, Table 1.5: The horizontal line that separates the unused bit combinations should be drawn immediately below the "9" row, one row higher than it is.

p. 31, Practice Exercise 1.8: "parity bit of A" should be "parity bit of ," .

p. 55, Answer to Practice Exercise 2.3: the gates in the logic diagram are correct, but the labels on the outputs of the two AND gates should be swapped.

p. 55, Practice Exercise 2.4: to match the Answers on the next page, the last gate in the logic diagram should be a NOR gate instead of an XOR gate.

p. 62, Answer to Practice Exercise 2.7: "F' = " should be "F = " (i.e., delete the prime on F).

p. 64, Answer to Practice Exercise 2.11: the last term should be "(x' + y' + z)" instead of "(x' + y + z')."

p. 64, Answer to Practice Exercise 2.12: the gates in the logic diagram are correct, but the label on the output of the last AND gate should be "ACD" instead of "ACD' " (i.e., delete the prime on D).

p. 80, Problem 2.32: This problem should not be marked with *, since no answer is given at the end of the book.

p. 93, Answer to Practice Exercise 3.5: there's a term missing from the answer: "x'y' + x'z" should be "x'y' + x'z + w."

p. 95, Answer to Practice Exercise 3.7: the list of prime implicants is correct but incomplete. Two more prime implicants that should be listed are w'z' and yz'.

p. 109, Answer to Practice Exercise 3.11: the gates in the logic diagram are correct, but the label on the output of the fourth NOR gate should be "(w'x + wx')' " instead of "(w'x wx')' " (i.e., insert a + symbol).

p. 135, fifth-to-last line: "end Simple_Circuit_vhdl" should be "end and_or_prop_delay_vhdl." And on the next line, "and_or_prop_delay_is" should be "and_or_prop_delay_vhdl is."

p. 136, third line: "and component" should be "end component."

p. 142, Problem 3.15: as printed, part (c) has no don't-care function and part (d) has two don't-care functions. To fix this, move "d(A, B, C, D) = Σ(3, 9, 11, 15)" from part (d) to part (c). Also change the moved don't-care function so that it reads "Σ(3, 9, 11)" instead of "Σ(3, 9, 11, 15)". This second change is necessary because minterm 15 is listed in the function F itself, so it cannot also be listed in the don't-care function.

p. 152, Practice Exercise 4.1: to match the Answer, in the logic diagram the second input of gate G4 should be connected to B instead of C.

p. 167, binary additions near the bottom of the page: in the right-hand addition, the carries should be "1 0" instead of "0 1" (i.e., there is no carry into the sign bit but there is a carry out of the sign bit).

p. 178, Practice Exercise 4.8: to match the Answer, delete "with active low enable."

p. 191, Figure 4.32: Delete "three-state gates" from the figure's caption.

p. 193, Answer to Practice Exercise 4.10 (Verilog): "D[0]=!(!A)" should be "D[0]=!((!A)" (i.e., insert another left parenthesis next to the first one).

p. 194, second architecture statement (about halfway down the page): "nand2_gate" should be "nand3_gate."

p. 195, Figure 4.33: inside the box labeled M7, "Not_mod" should be "Or_mod"; also, inside the box labeled M8, "Nor_mod" should be "Add_half."

p. 196, Figure 4.34(c): the input line labeled "g" should instead be labeled "a[0]."

p. 198, last line: "Add_half" should be "Add_half_vhdl." The same change should be made to the first line on p. 199.

p. 199, seventh line: "and component" should be "end component."

p. 199, line beginning with "M0" (about halfway down the page): "b" should be "w2," and "c_out" should be "w3." And on the next line (beginning with "M1"), "Add_half" should be "Add_half_vhdl." And in the port statement that begins three lines later, both instances of "bit_vector" should be "std_logic_vector." And in the component statement a few lines later, "Add_full_rca_vhdl" should be "Add_full_vhdl." And the port statement on the next line is completely wrong: it should be the same as the port portion of the entity statement for Add_full_vhdl earlier on this page, i.e., "port (a, b, c_in: in std_logic; c_out, sum: out std_logic)."

p. 200, sixth line: delete the semicolon at the end of this line (after "Add_rca_4_vhdl"). And four lines later, insert a semicolon at the end of the line (after "c_in4").

p. 200, thirteenth-to-last line: "half_adder_vhdl" should be "full_adder_vhdl." And three lines later, "x, y, z: in" should be "x, y: in."

p. 201, second line: the port portion of this statement is completely wrong: it should be the same as the port portion of the entity statement for full_adder_vhdl on the previous page, i.e., "port (S, C: out std_logic; x, y, z: in std_logic)."

p. 201, sixth through ninth lines: on each of these lines, "y = B" should be "y => B."

p. 201, tenth line: "ripple_carry_4_bit_adder_vhdl" should be "Structural."

p. 203, Answer to Practice Exercise 4.12--(VHDL): insert a semicolon at the end of the answer.

p. 207, fifth line of first full paragraph: "input port" should be "input or output port."

p. 210, Table 4.13: Five of the VHDL operators are typed incorrectly in the Symbol column. On the Relational row, "/ =" should be "/=", and "< =" should be "<=", and "> =" should be ">=" (i.e., in each of these, delete the space between the two characters.) On the Multiplication row, "·" should be "*". On the last row, "··" should be "**".

p. 289, third-to-last line: "from S0 to S1" should be "from S1 to S0."

p. 289, Figure 5.22: From time=0 to time=10, the waveform for t_x_in should be undefined rather than low. Also, the arrow by the words "Mealy glitch" points to the wrong place; it should point to the third pulse in the t_y_out waveform, not the second pulse.

p. 296, Figure 5.24: Assuming that this figure is generated using the same test bench as the previous Figure, then from time=0 to time=10, the waveform for t_x_in should be undefined rather than low. If t_x_in were truly low during this interval, then state and t_y_out would change from 0 to 1 at the first rising edge of clock.

p. 351, second line: "A0" should be "A1"; and on the next line, "from 1010(1010) to 1011(1110)" should be "from 1001(910) to 1010(1010)."

p. 357, fourth line: Delete "two serial inputs (shift_left, shift_right)."

p. 395, seventh line of first full paragraph: "Fig. 6.1" should be "Fig. 7.1."

p. 413, Figure 7.22: On the lower 4-input multiplexer, the inputs labeled F', G', and H' should be labeled G', H', and F', respectively.

p. 437, first line of first full paragraph: Delete "logic" from "arithmetic, logic, bitwise or reduction."

p. 465, fourth-to-last line of second paragraph: "clr_E. Depending" should be "clr_E, depending" (i.e., the period should be a comma). Also, on the next line, "is asserted, set_F" should be "is asserted. set_F" (i.e., the comma should be a period).

p. 466, Figure 8.11(b): In the second-to-last line of this Figure, "← 1" should be "← + 1," and vice versa in the last line. Also, in the last line, "S_2 → S_idle:" should be "S_2 → S_idle, set_F:".

p. 493, Figure 8.16(b): In the Register Operations column, "A <= Multiplicand" should be "B <= Multiplicand."

p. 497, third-to-last line: "three flip-flops" should be "two flip-flops."

p. 505, Figure 8.19: In the first of the two waveforms labeled Product[9:0], "2j3" should be "2f3"; also, "11b" should be "116".

p. 639, answer to Problem 1.33(c): "897" should be "871."

p. 641, answer to Problem 4.1(a): in the equation for F2, there should be a prime on D.

p. 641, answer to Problem 4.3(b): "4 columns" should be "14 columns."

p. 641, answer to Problem 4.8(a): The answer, which says that the 8-4-2-1 code and the BCD code are identical for digits 0 - 9, is true but irrelevant, since the problem specified the 8,4,-2,-1 code rather than the 8-4-2-1 code. The correct answer is: w = AB + AC′D′,  x = B′D + B′C + BC′D′,  y = CD′ + A′C′D,  z = D.

p. 648, answer to Problem 6.19(b): In the equation for DQ4, the last term should be Q'4Q2Q1 instead of Q'4Q'2Q1.